The present invention relates to updating temperature information of an on die thermal sensor (ODTS), and more particularly, to a temperature information output unit for updating temperature information of a semiconductor device according to a refresh period.
A dynamic random access memory (DRAM) cell includes a transistor for operating as a switch and a capacitor for storing a charge, i.e., data. According to whether the capacitor stores the charge, i.e., whether a terminal voltage of the capacitor is high or low, a logic level of the data is determined as a high level or a low level.
Since the data is stored in the capacitor as an accumulated electrical charge form, there is no power consumption for the data storage ideally. However, since there occurs a leakage current due to a PN junction of a metal oxide semiconductor (MOS) transistor, the stored initial charge may be discharged and, thus, the data may vanish.
To prevent data loss, the data stored in a memory cell is read and the read data is restored into the memory cell by recharging the memory cell with a normal charge before the data vanishes. This operation should be periodically performed in order to maintain data.
The above-mentioned recharging operation is called a refresh operation and, generally, a control of the refresh operation is performed by a DRAM controller. Due to the refresh operation, refresh power is consumed. In case of a battery operated system, which requires lower power consumption, reducing power consumption is very important and is a critical issue.
One method of reducing the power consumption for the refresh operation is changing a refresh period according to temperature. As the temperature decreases, a data holding time of the DRAM becomes longer. Therefore, by dividing a temperature range into several temperature regions and by lowering a frequency of a refresh clock at a relative low temperature region, power consumption is reduced.
Accordingly, a device for correctly sensing the temperature of the inside of the DRAM and for adjusting the refresh clock frequency is required.
As a semiconductor unit is highly integrated and is operated at a higher speed, a significant amount of heat is generated. The generated heat increases internal temperature of the semiconductor unit and, thus, can prevent the semiconductor unit from normally operating. The generated heat may cause a defect in the semiconductor unit.
Therefore, a device for correctly sensing the temperature of the semiconductor unit and for outputting the sensed temperature information is needed.
FIG. 1 is a block diagram of a conventional on die thermal sensor (ODTS) for use in a semiconductor device.
The conventional ODTS 1 includes a temperature sensing unit 2, an analog-to-digital converting unit 3, a temperature information converting unit 4, and an operating controller 5.
The temperature sensing unit 2 detects an internal temperature of the semiconductor device and generates a temperature voltage VTEMP according to the detected internal temperature. Further, the temperature sensing unit 2 outputs first and second variation voltages VULIMIT and VLLIMIT, which are upper and lower limits of the temperature voltage VTEMP, respectively.
The analog-to-digital converting unit 3 converts the temperature voltage VTEMP into a measuring temperature code DIGITAL_CODE having a digital value, and outputs an internal update signal IN_UPDATE.
The temperature information converting unit 4 performs a preset operation and converts the measuring temperature code DIGITAL_CODE into a temperature information code TEMP13 CODE and a plurality of flag signals TRIP_POINT_FLAG<0:M>, M being a positive integer, to output them with an update signal UPDATE in response to the internal update signal IN_UPDATE.
The operating controller 5 controls an operation on a normal mode of the ODTS 1 by receiving an impedance matching command ZQCAL_CMD from a memory register set (MRS) (not shown), controls an operation on a self-refresh mode of the ODTS 1 by receiving a self-refresh signal SREF, and controls an operation on a test mode of the ODTS 1 by receiving a test enable signal TEST_ENABLE.
A code storage unit 6 located at outside of the ODTS 1 stores the temperature information code TEMP_CODE in response to the update signal UPDATE. A memory controller can change a refresh period of the semiconductor device by reading the temperature information code TEMP_CODE stored by the code storage unit 6.
A self-refresh oscillation unit 7 located at outside of the ODTS 1 operates in the self-refresh mode and changes a self-refresh period of the semiconductor device in response to the plurality of flag signals TRIP_POINT_FLAG<0:M>.
An impedance matching unit 8 located at outside of the ODTS 1 operates under the control of the impedance matching command ZQCAL_CMD though the impedance matching unit 8 operates without regard to the ODTS 1.
FIG. 2 is a timing diagram showing an initialization operation of the conventional ODTS.
Hereinafter, referring to FIGS. 1 and 2, a sequence of the initialization operation of the conventional ODTS 1 is explained in detail.
First, if the impedance matching command ZQCAL_CMD is toggled, the initialization operation of the ODTS I starts.
Second, the operating controller 5 of the ODTS 1 activates a first operating control signal BGR_ON in response to the impedance matching command ZQCAL_CMD.
Third, the temperature sensing unit 2 initializes voltage levels of the temperature voltage VTEMP, and the first and second variation voltages VULIMIT and VLLIMIT in response to the first operating control signal BGR_ON. Herein, an activation time of the first operating control signal BGR_ON is preset by the operating controller 5.
Fourth, after finishing initializing the voltage levels of the temperature voltage VTEMP, and the first and second variation voltages VULIMIT and VLLIMIT of the temperature sensing unit 2, the operating controller 5 activates a second operating control signal ACT_ON.
Fifth, the analog-to-digital converting unit 3 of the ODTS 1 starts converting the temperature voltage VTEMP into the measuring temperature code DIGITAL_CODE as a digital value in response to the second operating control signal ACT_ON. The converting is repeatedly performed and the internal update signal IN_UPDATE is toggled with every converting. Herein, an activation time of the second operating control signal ACT_ON is preset by the operating controller 5.
Sixth, the temperature information converting unit 4 of the ODTS 1 converts the measuring temperature code DIGITAL_CODE into the temperature information code TEMP_CODE and the plurality of flag signals TRIP_POINT_FLAG<0:M>. The temperature information converting unit 4 drives the temperature information code TEMP_CODE and the update signal UPDATE in response to a toggling of the internal update signal IN_UPDATE. The temperature information converting unit 4 updates the temperature information code TEMP_CODE stored in the code storage unit 6 in response to the update signal UPDATE.
Further, each voltage level of the plurality of flag signals TRIP_POINT_FLAG<0:M> varies and is outputted according to the measuring temperature code DIGITAL_CODE regardless of toggling of the internal update signal IN_UPDATE. The temperature information converting unit 4 provides the self-refresh oscillation unit 7 operating in the self-refresh mode with the plurality of flag signals TRIP_POINT_FLAG<0:M> having temperature information so that the self-refresh period of the semiconductor device varies in response to the temperature.
Seventh, after the first and second operating control signals BGR_ON and ACT_ON are sequentially inactivated, the initialization operation of the ODTS 1 is finished.
The ODTS 1 updates the temperature information of the semiconductor device by repeatedly performing operations of the first step to the seventh step whenever the impedance matching command ZQCAL_CMD is toggled.
The impedance matching command ZQCAL_CMD is an output signal from the memory controller to the impedance matching unit 8 for matching impedances between input/output pins to transmit/receive data to/from the semiconductor device and transmission lines coupled to the input/output pins.
TABLE 1DDR3 800/1066/1333/1600SymbolMinMaxUnitstZQOper256NAtCK(formerly tZQXSR)tZQInit512NAtCK(formerly tZQCL)tZQCS64NAtCK
Table. 1 shows the impedance matching command ZQCAL_CMD specified in a specification of a double data rate III (DDR3) dynamic random access memory (DRAM) device manufactured by Intel Corporation.
Referring to Table. 1, the DRAM device cannot read and write data through the input/output pins for a predetermined time after the impedance matching command ZQCAL_CMD is inputted because the impedance matching command ZQCAL_CMD is used for matching impedances between the input/output pins and the transmission lines.
As a result, a bandwidth efficiency of the data input and output through the input/output pins is deteriorated. Accordingly, the DRAM device has a good performance when the impedance matching command ZQCAL_CMD is inputted at an interval of time as long as possible.
However, in the conventional ODTS 1, it is advantageous to update the temperature information at an interval of time as short as possible. That is, it is possible to accurately measure a temperature of the semiconductor device when the impedance matching command ZQCAL_CMD is frequently inputted at an interval of time as short as possible.
An update period of the temperature information of the ODTS 1 and an input period of the impedance matching command ZQCAL_CMD can be different from each other. This is because update period of the temperature information of the ODTS 1 varies according to the internal temperature of the DRAM device and the input period of the impedance matching command ZQCAL_CMD varies according to power noise of the DRAM device as well as the internal temperature of the DRAM device.
However, it is difficult for the conventional ODTS 1 to optimize each of the update period of the temperature information of the ODTS 1 and the input period of the impedance matching command ZQCAL_CMD because the conventional ODTS 1 updates the temperature information in response to the impedance matching command ZQCAL_CMD. As a result, the conventional ODTS 1 is difficult to perform an efficient operation.